Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the present invention relates to a semiconductor module with a plurality of interface circuits and a configuration for the self-test of interface circuits. The application furthermore relates to a method for the self-test of interface circuits of such a semiconductor module.
All semiconductor modules communicate with other devices via I/O interface circuits. With fast interface circuits, for example LVDS (Low-Voltage Differential Signals) or DDR (Double Data Rate), the necessary functional tests require a very high accuracy with regard to timing control and voltage.
The most widespread test method uses external test systems having very high accuracy with regard to timing control and voltage, which are connected via a multiplicity of signal lines to the modules to be tested. However, this procedure is increasingly encountering its limits, since test systems having the high accuracy required for the present-day fast interface circuits are very costly and in some instances are not commercially available with the required specification.
One possibility for dispensing with an external test system consists in providing an on-chip test logic with PLL (Phase-Locked Loop) or DLL (Delay-Locked Loop). However, this procedure is very complex and requires a very large chip area for the integration of the high-precision PLL or DLL test logic.
Published German patent application DE 198 32 307 A1 discloses an integrated circuit with a self-test device for the self-test of the integrated circuit, in which an output of the self-test device is connected via an output drive to an external contact-making point of the circuit, which, for its part, is connected via an input driver to the input of the circuit unit to be tested. In the test operating mode, the self-test device passes a test signal via the output driver to the contact-making point and from there via the input driver to the circuit to be tested.
German patent DE 199 01 460 C1 discloses an integrated semiconductor circuit with a plurality of pad cells which each comprise a terminal pad and an output driver and can be monitored in an operating mode of the circuit using a functional test. In this case, a signal generator generates periodic signal sequences which are fed to the pad cell and the transfer response of the pad cell is measured externally at the output of the cell in the frequency domain.
This marks the starting point for the invention.